MCS-51

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Getting started with MCS-51 development using free software: Dhrystone and Whetstone on the C8051F V2.1

This short tutorial shows how to compile the Dhrystone benchmark and execute it on an C8051F V2.1 board with an C8051F120 (the same board is also available with the C8051F020, which doesn't have enough RAM to run Dhrystone). The author used a Debian GNU/Linux system, but the tutorial should work for other Linux distributions, *BSD or other Unices.

The tools we use are

Hardware setup

C8051F V2.1 board with Dhrystone running

The C8051F V2.1 board is connected to the host computer via a U-EC6 to write the demo onto the board, while power is supplied via an extra cable. For serial ouput we attach a serial cable to the RS232 header.

Get SDCC

Depending on your operating system there might be an easy way to install SDCC 3.5.0 or newer using a package system or similar (e.g. apt-get install sdcc on Debian). While SDCC 3.4.0 should be sufficient for this tutorial, you might want to try a newer version in case you encounter any bugs.

SDCC binaries or a source tarball can be downloaded from its website.

Get ec2writeflash

ec2writeflash is part of the ec2-new package. The ec2-new source can be found at its GitHub location, where there is also a download link for a zip archive of the sources. To compile it, a C compiler, such as gcc, autotools and some necessary libraries need to be installed. Unzip the archive (e.g. using unzip stm8flash-master.zip) change into the directory stm8flash-master and type autoreconf; automake --add-missing; libtoolize; autoreconf; ./configure && make. In case there are any errors, such as header files not found, check that all necessary libraries are installed.

Get Dhrystone

Download a version of Dhrystone adapted for use with SDCC and the C8051F V2.1 board.
Download, and unpack it using tar -xzf dhrystone-c8051f120-uart0-sdcc-3.6.0.tar.gz, change into the directory dhrystone-c8051f120-uart0-sdcc-3.6.0.tar.gz.
You can then compile dhrystone by typing make. In the end there should be a file dhrystone.ihx.

A bit of custom code was necessary to make Dhrystone run using SDCC on the C8051F V2.1. See the file dhry.h and portme.c for details. The file portme.c basically combines clock() from the timer demo and putchar() from the serial demo. Since we are running a benchmark, and want good results, we run the C8051F120 at the maximum speed possible on the C8051F V2.1 board: 24.5 Mhz from the calibrated internal oscillator. The C8051F120 itself could run at up to 100 Mhz, but would require an external crystal to do so. While the C8051F V2.1 board has an external crystal, it runs at 22.184 Mhz only and is thus slower than the internal oscillator.

Put Dhrystone onto the board

Assuming the board is connected to a U-EC6 attached via USB, ec2writeflash --port USB --hex serial.ihx --run will write the demo onto the board. Dhrystone will run and report its results via UART0. You can see them by attaching a RS232 cable to the header on the board, and using a terminal program configured for 1200 baud, no parity, 8 bits, 1 stop bit and no flow control. They should look like this (the benchmark numbers may vary depending on the SDCC version used to compile Dhrystone):

Dhrystone Benchmark, Version 2.1 (Language: C)

Program compiled with 'register' attribute

Please give the number of runs through the benchmark: 
Execution starts, 20000 runs through Dhrystone
Execution ends

Final values of the variables used in the benchmark:

Int_Glob:            5
        should be:   5
Bool_Glob:           1
        should be:   1
Ch_1_Glob:           A
        should be:   A
Ch_2_Glob:           B
        should be:   B
Arr_1_Glob[8]:       7
        should be:   7
Arr_2_Glob[8][7]:    20010
        should be:   Number_Of_Runs + 10
Ptr_Glob->
  Ptr_Comp:          5133
        should be:   (implementation-dependent)
  Discr:             0
        should be:   0
  Enum_Comp:         2
        should be:   2
  Int_Comp:          17
        should be:   17
  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
        should be:   DHRYSTONE PROGRAM, SOME STRING
Next_Ptr_Glob->
  Ptr_Comp:          5133
        should be:   (implementation-dependent), same as above
  Discr:             0
        should be:   0
  Enum_Comp:         1
        should be:   1
  Int_Comp:          18
        should be:   18
  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
        should be:   DHRYSTONE PROGRAM, SOME STRING
Int_1_Loc:           5
        should be:   5
Int_2_Loc:           13
        should be:   13
Int_3_Loc:           7
        should be:   7
Enum_Loc:            1
        should be:   1
Str_1_Loc:           DHRYSTONE PROGRAM, 1'ST STRING
        should be:   DHRYSTONE PROGRAM, 1'ST STRING
Str_2_Loc:           DHRYSTONE PROGRAM, 2'ND STRING
        should be:   DHRYSTONE PROGRAM, 2'ND STRING

Microseconds for one run through Dhrystone: 582 
Dhrystones per Second:                      1717
Dhrystone Benchmark, Version 2.1 (Language: C)

Whetstone

Download a version of Whetstone adapted for use with SDCC and the C8051F V2.1 board.
, and proceed as with Dhrystone above. SDCC 3.6.0 does not support double. It replaces double by float and emits a warning to the user. Thus the scores from Whetstone obtained using SDCC 3.6.0 are not really comparable to those from other platforms. Unlike Dhrystone, Whetstone runs the benchmark before doing any text output, so don't worry when it takes some time until something appears on the terminal.

Loops: 10, Iterations: 1, Duration: 3583 msec.
C Converted Double Precision Whetstones: <NO FLOAT> KIPS

Since printf() does not have float support by default, you have to calculate the KIPS score from the data in the first row by hand: Multiply Loops by 100, divide by the duration in seconds. In this case we get a score of 279 KIPS.


More about ec2writeflash

ec2writeflash is part of ec2drv once written by Ricky White. Since ec2drv is no longer maintained, we use the version from the ec2-new fork.

More about SDCC

SDCC was initially written by Sandeep Dutta for the MCS-51, and has a relatively conservative architecture (see Sandeep Dutta, "Anatomy of a Compiler", 2000). It has been extended by various contributors and more recently, incorporated some cutting-edge technologies, in particular in register allocation (see Philipp Klaus Krause, "Optimal Register Allocation in Polynomial Time", 2013 and "Bytewise Register Allocation", 2015). However the mcs51 backend does not have all the fancy features and optimizations that some newer backends have.

SDCC is a C compiler that aims to be compliant with the C standards.

Important compiler options for MCS-51 developers include: